library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity rot13 is port (
                      letter_in: in std_logic_vector(7 downto 0);
                      letter_out: out std_logic_vector(7 downto 0) ;
                      clk, en: in std_logic
                      );
end rot13;

architecture behavioral of rot13 is
begin
  rot: 
  process (clk,en)
  begin
    if ((clk and en) = '1') then
      if ((letter_in > "01000000" AND letter_in < "01001110") OR
          (letter_in > "01100000" AND letter_in < "01101110")) then
        letter_out <= letter_in + "00001101";
      elsif ((letter_in > "01001101" AND letter_in < "01011011") OR
             (letter_in > "01101101" AND letter_in < "01111011")) then
        letter_out <= letter_in - "00001101";
      else
        letter_out <= letter_in;
      end if;
    end if;
  end process;