// behavioral rot13 in verilog
module rot13(in, out);
  input[7:0] in;
  output[7:0] out;
  reg[7:0] out;

  always @(in) begin
    if (in >= 8'h41 && in < 8'h4e || in >= 8'h61 && in < 8'h6e)
      out = in + 13;
    else if (in >= 8'h4e && in <= 8'h5a || in >= 8'h6e && in <= 8'h7a)
      out = in - 13;
    else
      out = in;
  end
endmodule

module main;
  // rot13 32Kb of data
  reg[7:0] mem[0:32768];
  reg[7:0] in;
  reg[8:0] i;
  wire[7:0] out;

  rot13 r(in, out);

  initial begin
    $readmemh("hexdump.dat", mem, 0, 32767);
    for (i = 0; mem[i] !== 8'bxxxxxxxx; i = i + 1) begin
      in = mem[i];
      #1 $write("%c", out);
    end
    $finish;
  end
endmodule