// structural verilog model to implement rot13
// uses a slow ripple carry adder, but is fairly small

module mux_2_1(out, in, select);
  output[7:0] out;
  input[15:0] in;
  input select;

  wire[7:0] anded_0, anded_1;

  not (select_bar, select);
  and a1[7:0] (anded_0, in[7:0], select_bar);
  and a2[7:0] (anded_1, in[15:8], select);
  or o[7:0] (out, anded_0, anded_1);
endmodule

// ripple carry adder
module adder5(out, a, b);
  output[4:0] out;
  input[4:0] a, b;

  wire[4:1] carry;
  wire[4:2] c_ab, c_ac, c_bc;

  and (c_ac[2], a[1], carry[1]);
  and (c_ac[3], a[2], carry[2]);
  and (c_ac[4], a[3], carry[3]);

  and (c_bc[2], carry[1], b[1]);
  and (c_bc[3], carry[2], b[2]);
  and (c_bc[4], carry[3], b[3]);

  and (carry[1], a[0], b[0]);
  and (c_ab[2], a[1], b[1]);
  and (c_ab[3], a[2], b[2]);
  and (c_ab[4], a[3], b[3]);

  or (carry[2], c_ab[2], c_ac[2], c_bc[2]);
  or (carry[3], c_ab[3], c_ac[3], c_bc[3]);
  or (carry[4], c_ab[4], c_ac[4], c_bc[4]);

  xor (out[0], a[0], b[0]);
  xor (out[1], a[1], b[1], carry[1]);
  xor (out[2], a[2], b[2], carry[2]);
  xor (out[3], a[3], b[3], carry[3]);
  xor (out[4], a[4], b[4], carry[4]);

  //initial $monitor("%b + %b = %b", a, b, out);
endmodule

// structural rot13
module s_rot13(out, in);
  input[7:0] in;
  output[7:0] out;

  wire[7:0] added, subtracted, rot13ed;
  wire[4:0] thirteen, minus_thirteen;

  assign thirteen = 5'b01101;
  assign minus_thirteen = 5'b10011;

  assign added[7:5] = in[7:5];
  assign subtracted[7:5] = in[7:5];

  //assign added[4:0] = in[4:0] + 13;
  //assign subtracted[4:0] = in[4:0] - 13;
  adder5 a(added[4:0], in[4:0], thirteen);
  adder5 s(subtracted[4:0], in[4:0], minus_thirteen);

  and (sub1, in[3], in[2], in[1]);
  or (sub, in[4], sub1);
  mux_2_1 op(rot13ed, {subtracted, added}, sub);

  and (mangle1, in[1], in[0]);
  or (mangle2, in[2], mangle1);
  and (mangle3, in[4], in[3]);
  and (mangle4, mangle2, mangle3);
  // this gate's awfully big
  nor (mangle5, in[4], in[3], in[2], in[1], in[0]);
  nor (mangle6, mangle4, mangle5);
  not (mangle7, in[7]);
  and (mangle, mangle7, in[6], mangle6);
  mux_2_1 m(out, {rot13ed, in}, mangle);
endmodule

module main;
  // rot13 32Kb of data
  reg[7:0] mem[0:32768];
  reg[7:0] in;
  reg[8:0] i;
  wire[7:0] out;

  s_rot13 r(out, in);

  initial begin
    $readmemh("hexdump.dat", mem, 0, 32767);
    for (i = 0; mem[i] !== 8'bxxxxxxxx && i < 32767; i = i + 1) begin
      in = mem[i];
      #1 $write("%c", out);
    end
    $finish;
  end
endmodule